module  top (
    input               clk,
    input               rst_n,
    input      [4:0]    sw,
    input               rx,
    // input       dq_in,
    // output      dq_out,
    // output      dq_en,
    inout               dq,
    output              tx,
    output     [0:0]    led,
    output     [5:0]    sel,
    output     [7:0]    dig,
    output              pwm
);

    wire                        en;
    wire                        dn;
    wire        [15:0]          temp_data;
    wire        [23:0]          dis_data;
    wire        [7:0]           data ; 

    reg                         din; 


always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        din <= 1'b0;
    end
    else if(data == 8'h80)begin
        din <= 1'b1;
    end
    else if(data == 8'hb3)begin
        din <= 1'b0;
    end
    else begin
        din <= din;
    end
end

ds18b20_driver   inst_ds18b20_driver (
       .clk     (clk),
       .rst_n   (rst_n),
       .sw      (sw),
    //    .dq_in   (dq_in),
    //    .dq_out  (dq_out),
    //    .dq_en   (dq_en),
       .dq      (dq),
       .temp_data(temp_data)
); 

ctrl            inst_ctrl (
    .t_data     (temp_data),
    .dis_data   (dis_data),
    .sw         (sw),
    .en         (en),
    .dn         (dn)
);

sel_driver      inst_sel_driver (
    .clk        (clk),
    .rst_n      (rst_n),
    .dis_data   (dis_data),
    .sw         (sw),
    .sel        (sel),
    .dig        (dig)
);

beep             inst_beep (
    .clk        (clk),
    .rst_n      (rst_n),
    .en         (en),
    .dn         (dn),
    .din        (din),
    .pwm        (pwm)
);

uart_loop       inst_uart_loop (
    .clk        (clk),
    .rst_n      (rst_n),
    .rx         (rx),
    .sw         (sw),
    .data       (data),
    .tx         (tx)
);

led             inst_led (
    .clk        (clk),
    .rst_n      (rst_n),
    .din        (din),
    .led        (led)
);
endmodule